Fast Low-Energy VLSI Binary Addition

This paper presents novel architectures for fast binary addition which can be implemented using multi-plexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and re-casting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wt fa to Wt mux where t fa and t mux , respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carry-generation component is the critical component in redundant-to-binary conversion and binary addition. It is shown that fastest binary addition can be performed using (W log 2 W + W + 1) multiplexers in time (log 2 W + 2)t mux. If the speciied adder latency is greater than (log 2 W +2)t mux , then a family of converters using fewest multiplexers can be designed based on carry-select approach. Finally a class of hybrid adders are designed by using a carry-select connguration and by substituting tree-based blocks in place of some carry-select blocks. It is shown that this approach can lead to adder designs which consume the least energy.